frequency range operating temperature storage temperature overall frequency stability supply voltage (vdd) jitter (12khz - 20mhz) abracon is a b r a c o n i s iso 9001 / qs 9000 i s o 9 0 0 1 / q s 9 0 0 0 certified c e r t i f i e d abracon is iso 9001 / qs 9000 certified 30332 esperanza, rancho santa margarita, california 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com ceramic smd crystal clock oscillator c e r a m i c s m d c r y s t a l c l o c k o s c i l l a t o r ceramic smd crystal clock oscillator ||||||||||||||| abfm series standard specifications: applications: fiber channel 12gbit serdes 10gbit serdes pci express features: based on a proprietary analog multiplier tri-state output ultra low phase jitter 125mhz, 156.25mhz, 187.5mhz, and 212.5mhz applications 2.5v to 3.3v +/- 10% operation ceramic smd, low profile package rev3.1-8/06 parameters 150 mhz to 280 mhz 0c to + 70c (see options) - 55c to + 125c 50 ppm max. (see options) 2.25v - 3.63 v rms phase jitter < 0.3ps period jitter < 20ps peak to peak typical low phase noise aging (ppm/year) -130 dbc/hz @ 1khz offset from 212.5mhz -140 dbc/hz @ 10khz offset from 212.5mhz -145 dbc/hz @ 100khz offset from 212.5mhz tbd per crystal 5.0 x 7.0 x 1.8mm supply current (i dd )[fout = 212.50mhz] output clock duty cycle @ v dd -1.3v output high voltage output low voltage clock rise time (t r ) @ 20/80% clock fall time (t f ) @ 80/20% 85ma max. 45% min, 50% typical, 55% max. v oh = (vdd-1.025v min) v ol = (vdd-1.620v max) 0.2ns typical, 0.5ns max, 0.2ns typical, 0.5ns max supply current (i dd ) [fout = 212.50mhz] output clock duty cycle @ 1.25v output differential voltage (v od ) vdd magnitude change ( ? v od ) output high voltage output low voltage offset voltage [r l = 100 ? ] offset magnitude voltage[rl = 100 ? ] power-off leakage (i oxd ) [vout=vdd or gnd, vdd=0v] output short circuit current (i osd ) differential clock rise time (t r ) [r l =100 ? , cl=10pf] differential clock fall time (t f ) [r l =100 ? , cl=10pf] 55ma typical, 60ma max 45% min, 50% typical, 55% max 247mv min, 355mv typical, 454mv max -50mv min, 50mv max v oh = 1.4v typical,1.6v max v ol = 0.9v min, 1.1v typical v os = 1.125v min, 1.2v typical, 1.375v max ? v os = 0mv min, 3mv typical, 25mv max 1 a typical, 10 a max -5ma typ, -8ma max. 0.2ns min, 0.5ns typical, 0.7ns max 0.2ns min, 0.5ns typical, 0.7ns max : preliminary
abracon is a b r a c o n i s iso 9001 / qs 9000 i s o 9 0 0 1 / q s 9 0 0 0 certified c e r t i f i e d abracon is iso 9001 / qs 9000 certified 30332 esperanza, rancho santa margarita, california 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com ||||||||||||||| abfm series ceramic smd crystal clock oscillator c e r a m i c s m d c r y s t a l c l o c k o s c i l l a t o r ceramic smd crystal clock oscillator dimensions: inch (mm) marking: - tuh frequency: t=first ?ten? digit of frequency, u=first ?unit? of frequency, h=first ?tenth? digit of freq, ex: 100 for 10.0mhz; 143 for 14.31818 mhz) - abfm zyx (z: month, a to l; y: year, 5 for 2005; x: traceability code) pin assignments: standard specifications: options and part identification (left blank if standard) : pecl & lvds drawing: dimensions: inch (mm) cmos drawing: abfm x - frequency - temperature - frequency stability - output - tri-state pin output - packaging packaging option: t for tape and reel (1,000pcs/reel) t5 for tape and reel (500pcs/reel) pin # name description 1 2 3 4 5 6 tri-state nc gnd q q v dd tri-state no connect ground pecl, lvds complimentary pecl, lvds vdd connection tri-state pin operation: output type option pin 1 logic level* output state p p1 v c pecl pecl1 lvds cmos 0 (default) 1 1 0 0 1 (default) 0 1 (default) enabled tri-state enabled tri-state tri-state enabled tri-state enabled *connect to vdd from logic level "1", connect to ground for logic level "0". stability options: r for 25 ppm max vdd options: pin # name 1 2 3 4 tri-state gnd/case output vdd supply current (i dd )[at 100mhz, load 15pf] output clock duty cycle @ 50%v dd output high voltage (v oh ) [i oh = -8.5ma] output low voltage (v ol ) [i ol = 8.5ma] output drive current (i osd ) [v ol = 0.4v, v oh = 2.4v] output clock rise/fall time [10% ~ 90% vdd w/10pf load] output clock duty cycle [measured @ 50% vdd] 16ma typ., 20ma max. 45% min, 50% typical, 55% max. 2.4 min 0.4v max 8.5ma typ. 1.2ns typical, 1.6ns max. 45% min, 50% typical, 55% max. blank (3.3vdc10%v) 1 (2.5vdc10%v) rev3.1-8/06 5.0 x 7.0 x 1.8mm : preliminary
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